The invention pertains to clock distribution, particularly within an integrated circuit (IC).
Most high speed integrated circuits (ICs) utilize some form of delay-locked loop (DLL) for the creation of internal clocks. A DLL removes the insertion delay from an IC""s internal clocks so that the delays associated with clocks received at an IC""s register elements match the delays associated with an external clock received at the IC""s external contacts. Delays which can be matched include delays which affect phase alignment, and delays which affect frequency.
A DLL removes insertion delay using a delay comparator and correction unit. The delay comparator and correction unit receives first and second clocks, one of which is derived from an input clock, and one of which is derived from a feedback clock. In response to these clocks, the delay comparator and correction unit generates a delay-corrected clock and the afore-mentioned feedback clock. The delay-corrected clock is then distributed to an IC""s register elements via a clock distribution network, and the feedback clock is routed back into the delay comparator and correction unit via a feedback circuit comprising a string of invertors. If the feedback circuit is constructed such that its delay equals the sum of 1) the delay incurred in routing a clock signal through the clock distribution circuit, 2) the delay incurred in receiving, buffering and inputting the input clock into the delay comparator and correction unit, and 3) the delay through the delay comparator and correction unit, then the delays associated with clocks received at the IC""s register elements will substantially match the delays associated with the input clock.
A first preferred embodiment of apparatus for distributing clocks comprises first and second differential receivers, a delay comparator and correction unit, and a feedback circuit. The structures of the first and second differential receivers are substantially matched, with the first differential receiver receiving a differential input clock and outputting a first clock, and with the second differential receiver receiving a differential feedback clock and outputting a second clock. The first and second clocks are received by the delay comparator and correction unit, and in response thereto, the delay comparator and correction unit generates a delay-corrected clock and a feedback clock. The feedback circuit comprises 1) a first signal route for carrying the feedback clock from the delay comparator and correction unit, 2) a converter for converting the feedback clock into the afore-mentioned differential feedback clock, and 3) a second signal route for coupling the converter to the second differential receiver.
A second preferred embodiment of apparatus for distributing clocks comprises first and second differential receivers, a delay comparator and correction unit, and a feedback circuit. The structures of the first and second differential receivers are substantially matched, with the first differential receiver receiving a differential input clock and outputting a first clock, and with the second differential receiver receiving a differential feedback clock and outputting a second clock. The first and second clocks are received by the delay comparator and correction unit, and in response thereto, the delay comparator and correction unit generates a differential delay-corrected clock and a differential feedback clock. The feedback circuit carries the differential feedback clock from the delay comparator and correction unit to the second differential receiver.
A first preferred embodiment of a method for distributing clocks commences with providing first and second differential receivers with substantially matched structures. A differential input clock is then received at the first differential receiver, and a differential feedback clock is received at the second differential receiver. Clocks which are output from the first and second differential receivers are then compared and, in response thereto, a delay-corrected clock and a feedback clock are generated. The feedback clock is then converted to the differential feedback clock.
A second preferred embodiment of a method for distributing clocks commences with providing first and second differential receivers with substantially matched structures. A differential input clock is then received at the first differential receiver, and a differential feedback clock is received at the second differential receiver. Clocks which are output from the first and second differential receivers are then compared and, in response thereto, a differential delay-corrected clock and the afore-mentioned differential feedback clock are generated.